碩士研究生的英文簡(jiǎn)歷

時(shí)間：2024-08-30 19:41:41 英文簡(jiǎn)歷我要投稿

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碩士研究生的英文簡(jiǎn)歷

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luBin wangMale, born in 1980.1Signal and Information ProcessingXidian University, Xi’an, Shaanxi, China.TEL:Email: Job Desired Signal Processing Algorithm Engineer Electronic engineer with emphasis _disibledevent=EN-US style="FONT-SIZE: 10.5pt; FONT-FAMILY: Verdana">FPGA design and developmentEducation9/2005– now M.S., Signal and Information Processing, Xidian University9/1998-7/2002 B.S., Electronic Information Engineering, Yanshan UniversityLanguageEnglish (CET-6)Especially adept at reading and writing English material for researchingExperience, Knowledge Computer knowledge: Windows, LINUX, MS Office Software Team oriented, love to work in highly motivated teams Good communication skills In-depth understanding of special knowledge in the field of Signal and Information Processing Programming skills: good experience in C and assembly programming languages for signal processing Full competence in the design of digital filter and filter banks Experience of system simulation with MATLAB Skilled in using FPGA and Verilog-HDL for designing digital system, especially have a profound understanding of the algorithms implemented with FPGA for Digital Down-sampling Converter (DDC), Digital Up-sampling Converter (DUC) and Crest Factor Reduction (CFR) Familiar with TD-SCDMA. Participated in the research and development of ZXTR R01 (Remote Radio Unit in the TD-SCDMA communication system) in the Xi’an R&D Center of ZTE among recently 10 months. Completed the FPGA designing and debugging of this systemPublications 《An Efficient Algorithm for Designing Cosine Modulated Filter Banks with Linear Phase Satisfy Perfect Reconstruction》 ICCCAS 2007 2007.7 (indexed by EI) 《An Efficient Weighted Lp Algorithm for the Design of Non-uniform Filter Banks》ISPACS 2007 2007.10 (indexed by EI)

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